Optimized DC booster charge pump in 180 nm CMOS technology suitable for radar and RFID applications

Document Type : Original Article

Authors

1 PhD student, Faculty of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran

2 Assistant Professor, Faculty of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran

Abstract

In this paper, a new charge pump in CMOS technology is designed and implemented. By using the body bias to reduce the threshold voltage and controlling the voltage by using the voltage reference circuit, a DC to DC voltage booster circuit with high efficiency has been achieved to provide an input voltage of 320 millivolts and an output voltage of more than 1 volt. Simulations have been done so that the proposed voltage booster circuit can be analyzed in a state where the results are close to the fabrication results. The results indicate that compared to previous works, smaller capacitors have been used to reduce the area of the circuit as well as high output voltage by using the minimum number of transistors. The simulation results with 25 pF charge pump capacitor in each clock pulse frequency of 200 kHz show that the input voltage of 350 millivolts reaches 1.2 volts in less than 2 milliseconds. The proposed circuit can be suitable for radar and RFID applications with low power consumption.

Keywords

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References

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History

  • Receive Date: 22 April 2022
  • Revise Date: 20 June 2022
  • Accept Date: 24 July 2022
  • Publish Date: 21 September 2022

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