A High sensitive Envelope Detector with Very Low Transition Time Using 180 nm CMOS Technology for RADAR Applications

Document Type : Original Article

Authors

1 Master's student, Shahrekord University, Shahrekord, Iran

2 Assistant Professor, Shahrekord University, Shahrekord, Iran

Abstract

This paper presents a high-sensitive envelope detector in 2.7GHz to 3.9GHz frequency band using 180 nm CMOS technology. The detector is based on the Successive Detection Logarithmic Amplifiers (SDLA) and consists of three sections: the detector core (rectifier), semi-logarithmic RF amplifier, and output stage. The detector core is based on the unbalanced source coupled method, which provides a full-wave rectifier. The frequency bandwidth and transition time of detector core are 0.1GHz to 10 GHz and 1ns, respectively. In this paper, the sensitivity of the detector is also improved about 2 dB by injecting part of the input signal into the tail current path. To amplify the signal, a proposed low-noise amplifier(LNA) with a single input and differential output and a simple differential amplifier in series are used. The output stage provides a low pass filter and drives a 2pF output capacitance, without increasing the transition time. By using RF power limiters in the outputs of LNA and differential amplifier, a semi-logarithmic behavior for the total circuit is obtained while preventing saturation of amplifiers due to the large input signal. Post-layout simulation results by Spectre-RF show the sensitivity of -45dBm and the rise and fall times of less than 1.2ns, which is a significant improvement compared to recent reported work. The semi-logarithmic dynamic range and the power consumption of this detector are 20dB and 12mW from a voltage source of 1.8V, respectively. The occupied area of the detector core is only 72µm×72µm, while the active area of the total detector, including amplifiers, limiters, rectifiers and output buffer is 0.7mm×0.55mm.

Keywords


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Volume 9, Issue 2 - Serial Number 26
November 2022
Pages 15-23
  • Receive Date: 04 March 2021
  • Revise Date: 20 November 2021
  • Accept Date: 01 October 2022
  • Publish Date: 22 November 2022