Design and implementation of a frequency synthesizer based on phase-locked loop for using in radar applications

Document Type : Original Article

Authors

1 Master's degree, Malek Ashtar University of Technology, Tehran, Iran

2 Associate Professor, Malek Ashtar University of Technology, Tehran, Iran

Abstract

In most telecommunications and radar receivers, one or more local oscillators are used to convert the input frequency to the intermediate frequency. In an ideal receiver, this frequency conversion does not distort the input signal, and all the information on the signal can be recovered. In a real receiver, both the mixer used to convert the signal frequency and the local oscillator distort the signal, limiting the receiver's ability to recover the signal. Degradation caused by the mixer, such as undesirable mixed outputs, can be minimized by proper design in the rest of the receiver. The destruction caused by the local oscillator, which is usually random phase changes or phase noise, cannot be reduced except by improving the performance of the oscillator. The purpose of this paper is to design and implement a frequency synthesizer based on a phase-locked loop. The frequency synthesizer unit is used in all types of frequency-domain and time-domain radars. In frequency domain radars, the frequency synthesizer circuit can be used as a waveform generator or to generate a local oscillator signal. Also, in time-domain radars, with the aim of synchronizing different parts of the radar, a frequency synthesizer circuit is used. In this paper, a frequency synthesizer based on a phase-locked loop named ADF4350 is used. The output frequency of this part is set to 1 GHz. The circuit design of this part is done in ADIsimPLL software, and its board is drawn in Altium Designer software. In order to check more carefully before implementation, the phase-locked loop circuit is also simulated in ADS software. After design, the frequency synthesizer board has been built along with the power supply board, and the phase noise results have been measured. The measured phase noise matches the values in the datasheet for the part.

Highlights

 [1] C. J. Grebenkemper, “Local oscillator phase noise and its effect on receiver performance,” Watkins-Johnson Company Tech-notes, Vol. 8, No. 6, 1981.

[2] I. Collins, “Phase-Locked Loop (PLL) Fundamentals,” SSB, Vol. 130, No. 140, p. 150, 2018.

[3] Analog Device, “Fundamentals of Direct Digital Synthesis (DDS),” https://www.analog.com/MT-085, 2009.

[4] Analog Device, “Section 8. Replacing or Integrating PLL's with DDS Solutions,” https://www.analog.com/media/en/training-seminars/design-handbooks/Technical-Tutorial -DDS, 1999.

[5] H. Wang and D. Guo and L. Wang, “Design and implementation of Ku-band frequency synthesizer,” International Conference on Integrated Circuits and Microsystems, 2016, doi: 10.1109/ICAM.2016.7813570.

 [6] M. Stork, “Software Implementation of a Simple All-Digital Frequency Synthesizer,” 12th Mediterranean Conference on Embedded Computing (MECO), 2023, doi: 10.1109/MECO58584.2023.10154909.

Keywords


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 [1] C. J. Grebenkemper, “Local oscillator phase noise and its effect on receiver performance,” Watkins-Johnson Company Tech-notes, Vol. 8, No. 6, 1981.
[2] I. Collins, “Phase-Locked Loop (PLL) Fundamentals,” SSB, Vol. 130, No. 140, p. 150, 2018.
[3] Analog Device, “Fundamentals of Direct Digital Synthesis (DDS),” https://www.analog.com/MT-085, 2009.
[4] Analog Device, “Section 8. Replacing or Integrating PLL's with DDS Solutions,” https://www.analog.com/media/en/training-seminars/design-handbooks/Technical-Tutorial -DDS, 1999.
[5] H. Wang and D. Guo and L. Wang, “Design and implementation of Ku-band frequency synthesizer,” International Conference on Integrated Circuits and Microsystems, 2016, doi: 10.1109/ICAM.2016.7813570.
 [6] M. Stork, “Software Implementation of a Simple All-Digital Frequency Synthesizer,” 12th Mediterranean Conference on Embedded Computing (MECO), 2023, doi: 10.1109/MECO58584.2023.10154909.
Volume 11, Issue 2
Serial number 30, Autumn and Winter
January 2024
Pages 1-8
  • Receive Date: 08 October 2023
  • Revise Date: 14 December 2023
  • Accept Date: 27 December 2023
  • Publish Date: 21 January 2024