Presenting an Optimal Method of a Fractional-N Synthesizer to Reduce the Power Consumption of the Phase-Locked Loop with Delta-Sigma Modulator in x-Band Radars

Document Type : Original Article

Authors

1 PhD student, Shahid Sattari University of Aeronautical Sciences and Arts, Tehran, Iran

2 Faculty of Electrical Engineering, Imam Hossein Comprehensive University, Tehran, Iran

3 PhD, Shahid Sattari University of Aeronautical Sciences and Technology, Tehran, Iran

Abstract

Increasing demand for the integration of wide circuits with low cost, and performance with low power consumption in the form of a chip has become one of the most important issues of the day for designers. Therefore, many efforts have been made to build RF integrated circuits and systems in the GHz frequency range using CMOS technology. The use of frequency synthesizers based on phase lock loops is one of the most important building blocks of a function generator, which has the task of producing the carrier signal and is one of the most important and sensitive function blocks of the generator; Because it works at high frequencies and the contribution of its power consumption in the generator function is high. This research has implemented a design and simulation of a frequency synthesizer for use in X-band radars. The results of this research show that the newly designed linearization technique of CP currents has a high compliance compared to the CP current without linearization technique, and the maximum mismatch is about 0.4 microseconds in the control voltage between 0.2 and 1.6 volts. The designed fractional-N power consumption is about 6.579 μW with a 1.8 V power supply. In the synthesizer. The phase noise of the VCO with a carrier frequency of 10 GHz, at an offset of 1 MHz is equal to -106 dBc/Hz. The power of the sideband sources is 55 dBc - shorter than the carrier signal (at a frequency of 10.004 GHz) it arrives.

Keywords

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References

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Radar
Volume 11, Issue 1
Serial number 29, spring and summer quarterly
August 2023

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History

  • Receive Date: 22 May 2023
  • Revise Date: 29 June 2023
  • Accept Date: 04 August 2023
  • Publish Date: 23 August 2023

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